The IPO buys scale, not the memory tier carrying today’s shortage profits. The CXMT IPO priced this week as the largest listing in the history of Shanghai’s STAR Market, and retail investors put in orders for roughly 212 times the shares on offer. The company can already supply substantial commodity DRAM, but not yet the HBM and fast server DDR5 driving the shortage’s profits.
The IPO settles the scale question, not the competitiveness question
ChangXin Memory Technologies, China’s only volume DRAM maker, debuted on the STAR Market on July 27, 2026 at 8.66 yuan a share. Seoul Economic Daily reported a valuation of about 580 billion yuan, roughly $80 billion, and proceeds on the order of $8-9 billion, making it the largest listing since the STAR board opened. Retail demand was equally conspicuous: the report counted about 9.4 million applications and oversubscription of roughly 212 to one.
Those figures settle whether CXMT can attract capital. They do not settle what that capital can produce economically.
The demand side is not theoretical. Reported multi-year agreements include about $7 billion of supply for ByteDance and $3 billion for Tencent. Consumer names associated with CXMT include Corsair and, according to Citrini Research as cited by TweakTown, Apple. The contracts give new capacity a domestic destination and reduce the risk that every additional wafer must immediately compete in an open global market.
The physical expansion is also substantial. Citrini Research estimates that CXMT will grow from about 40,000 DRAM wafer starts per month in 2020 to roughly 350,000 by the end of 2026, an increase of nearly 775%. SemiAnalysis gives the same year-end estimate and compares it with roughly 380,000 wafer starts per month for Micron. On capacity alone, that would put CXMT within reach of the third-largest DRAM producer.
The broader buildout extends beyond CXMT. The cited estimate for CXMT, JHICC, Swaysure and YMTC reaches about 1.41 million monthly wafer starts by 2030, potentially making China the second-largest DRAM production base after South Korea. This removes a genuine bottleneck: China’s shortage of domestic memory fabrication capacity.
Yet the bottleneck moves as soon as those fabs are funded. Capacity measures wafers entering production. Customers pay for usable bits with the right speed, power, reliability and qualification. Investors ultimately care about the margin earned on those bits. CXMT’s wafer count cannot answer either question by itself.
The listing also arrives amid an unresolved legal dispute involving the three incumbents. A US class action filed June 25, 2026 accuses Samsung, SK Hynix and Micron, together about 90% of the DRAM market, of coordinating a shift toward HBM while curtailing DDR3 and DDR4. The plaintiffs allege that prices rose about 700% over four years. Those are allegations, not established facts, and Micron denies them. The dispute explains why buyers may welcome a credible fourth supplier, but it does not prove that CXMT can compete in the same product and profit tiers.
Wafer capacity becomes a yield and cost bottleneck
The first correction to the capacity narrative comes from bit output. SemiAnalysis estimates that CXMT held about 11% of global DRAM wafer capacity in 2025 but shipped about 9% of global bits. For 2027, it projects about 17% of capacity against about 12% of bits. Dividing bit share by capacity share produces a ratio of about 0.82 for 2025 and 0.71 for 2027. That is my calculation from SemiAnalysis’s estimates, not a company disclosure.
The direction matters more than the decimal. CXMT’s installed capacity is projected to rise faster than its saleable bit output. Adding fields does not produce an equal harvest when each field yields less.
Most of CXMT’s 2026 output is on its G4 process, described by SemiAnalysis as comparable to the incumbents’ 1z generation. Its yields reportedly remain below the mature-industry range of 85-90%. G5, a 1a-equivalent process, introduces greater design and fabrication difficulty. These are analyst characterizations rather than CXMT-reported manufacturing statistics, but they identify the next constraint clearly: the number of good dies obtained from each wafer.
An older node has a direct cost consequence. A DRAM cell combines a capacitor and transistor. When a process cannot pack as many cells into the same silicon area, a die of a given capacity is larger. Fewer potential dies fit on a wafer, and yield losses remove a further portion. More wafer starts can compensate for part of that deficit, but only by consuming more fab time, process materials and capital for each good bit.
On DDR5, SemiAnalysis estimates CXMT’s cost per bit at more than 30% above the three leaders. In the first quarter of 2026, however, shortage conditions reportedly allowed CXMT’s selling prices to sit only about 5-10% below incumbent prices. That spread is favorable while supply is tight: the market price hides much of the production disadvantage.
It will not necessarily hide it for the life of the fabs financed by this IPO. When supply loosens and average selling prices fall, CXMT faces three choices: close the node and yield gap, accept lower margins, or pull back from price-led expansion. The IPO solves the capital bottleneck and creates a utilization problem if the new lines cannot produce enough competitive bits per wafer.
The profitable tier remains behind the HBM gate
Yield and cost become even more restrictive in the products carrying today’s highest margins. SemiAnalysis estimates that roughly 99% of CXMT’s 2025 revenue came from conventional DDR and LPDDR, with HBM contributing minimally. It also estimates first-quarter 2026 DRAM operating margins near 73% for SK Hynix, 81% for Samsung and 84% for Micron, supported largely by HBM and high-speed server DDR5. These are third-party estimates, not reported product-level margins.
That product distinction is the center of the thesis. CXMT can add bits to the commodity majority of the market without relieving the shortage in the tier attached to AI accelerators. HBM and fast server DDR5 carry different process, packaging and qualification demands. The same pressure has pushed inference chips toward LPDDR5X, but substitution does not make conventional DDR equivalent to qualified accelerator memory.
The IPO prospectus, as summarized by SemiAnalysis, directs most proceeds toward DRAM line upgrades and forward DRAM research. No HBM line was specifically disclosed in that summary. Even if funding eventually reaches HBM, equipment access places a ceiling over the front end. CXMT scales with DUV multipatterning rather than EUV because export controls keep extreme-ultraviolet lithography tools out of reach.
DUV multipatterning can extend a process, but each additional patterning sequence means more masks, exposures, deposition and etch steps. That raises equipment use, cycle time, defect opportunities and cost. It remains a workable route for commodity production. At the leading edge, it makes the effort to improve density and cost progressively harder.
HBM adds another bottleneck after the wafer leaves the front end. Eight or twelve DRAM dies must be stacked and connected through silicon vias. The package is commercially useful only when the component dies and the assembly work together. Yield therefore compounds across fabrication, wafer sort, bonding and final assembly.
SemiAnalysis models CXMT’s HBM3 8-high overall yield at roughly 25%, with front-end wafer-sort yield near 35% and back-end assembly yield near 70%. It also reports difficulty moving from 8-high to 12-high and a growing possibility that CXMT skips HBM3 for HBM3E. Korean reporting describes CXMT’s HBM performance as years behind. All of those points are reported assessments or estimates, not CXMT disclosures.
The commercial sequence matters. An installed HBM line is not a qualified HBM supplier. Qualification at one customer is not proof of broad adoption. A qualified stack is not a high-margin product unless yields and costs support volume delivery. CXMT is still confronting those gates. IPO proceeds can finance more experiments and equipment, but cash alone cannot deliver EUV access, compound stack yield or customer approval.
Who captures the value, and who carries the risk
The expansion does not have one winner. It redistributes value and risk by product tier.
PC and consumer buyers are positioned to capture the earliest price benefit. Module makers, Corsair and Apple’s supply chain gain another potential source of DDR4, LPDDR and entry DDR5. That could eventually ease the DRAM shortage that has repriced consumer memory. The relief is most plausible in low-to-mid tiers, where CXMT already has output, rather than in HBM.
Chinese cloud and AI customers capture a different kind of value. ByteDance and Tencent can treat domestic memory as a supply-security hedge. Huawei and Cambricon are plausible first customers if CXMT advances into accelerator memory. Domestic contracts can absorb capacity even before CXMT becomes globally cost leading, turning part of the investment into a resilience program rather than a pure price war.
Samsung, SK Hynix and Micron carry the risk of weaker commodity pricing and reduced discipline in what has been a three-supplier market. They do not yet face the same degree of threat in HBM. On the evidence available here, their yield, node and qualification advantages continue to protect the high-margin tier.
Equipment suppliers such as ASML, Applied Materials and Lam can benefit from a large and durable fab buildout. CXMT needs DUV lithography, deposition, etch and multipatterning capacity as it adds wafers and attempts node transitions. Export restrictions limit which tools can be supplied, however, and that restriction shapes both the revenue opportunity and the ceiling on CXMT’s process roadmap.
CXMT and its investors own the central execution risk. The company must turn financing into good bits, turn good bits into qualified products and do both at a cost that survives lower selling prices. If the shortage persists, strong prices can extend the adjustment period. If it ends before yield and cost improve, new capacity may amplify the weakness it was meant to solve.
The three signals that decide whether scale becomes competition
- DDR5 cost per bit. The central benchmark is the reported gap of more than 30% against the incumbents. If independent analysis shows that gap approaching 10% before 2027, CXMT is moving from capacity expansion toward genuine competitiveness. If it remains above 30% as selling prices normalize, the new fabs are commodity ballast rather than margin-equivalent capacity.
- HBM qualification and stack yield. A named volume qualification at Huawei, Cambricon or another accelerator customer would matter more than an announcement that a line exists. The stronger signal would pair qualification with evidence that overall yield has moved materially beyond the modeled 25% for HBM3 8-high.
- Post-shortage pricing and utilization. SemiAnalysis expects DRAM undersupply in the high-single-digit percentage range in 2026, widening toward the low-to-mid teens in 2027. When that condition loosens, CXMT’s selling prices and fab utilization will reveal whether domestic contracts, manufacturing progress and cost reductions are sufficient to support the added capacity.
The most likely near-term paths are commodity repricing and domestic substitution. CXMT and its peers can add enough DDR4, LPDDR and entry DDR5 to pressure lower-tier pricing or backfill Chinese demand without immediately breaking the incumbents’ HBM franchise. Genuine disruption of the profitable tier requires CXMT to close the DDR5 cost gap, scale a more advanced node without EUV, achieve commercially viable HBM stack yield and complete customer qualification.
The most useful way to read the listing is therefore as a test of a common mistake: pricing capacity as if it were competitiveness. CXMT is a real fourth force in DRAM, and its financing can reshape the commodity end of the market. But the memory carrying extraordinary margins is not yet the memory CXMT can make at comparable yield, cost and qualification.
The decisive figure is not the wafer count quoted around the IPO. It is CXMT’s DDR5 cost per bit after shortage pricing stops hiding the gap. The IPO buys more factories. It does not yet buy the product the market pays extraordinary prices for.
This article is for informational and educational purposes only and does not constitute investment, financial, or legal advice.
Sources
- newsletter.semianalysis.com — CXMT capacity vs incumbents, capacity vs bit share, DDR5 cost gap, product mix, HBM yield, node status, incumbent margins, undersupply outlook, use of proceeds (2026-06-23)
- tweaktown.com — 350k vs 380k wspm, 40k in 2020, China 1.41M by 2030 with JHICC/Swaysure/YMTC, DDR5-8000, DUV multipatterning not EUV, Corsair/Apple customers (Citrini Research) (2026-07-17)
- en.sedaily.com — STAR Market listing July 27, 8.66 yuan, ~580B yuan valuation, largest STAR listing, ~212:1 retail oversubscription, ByteDance/Tencent contracts, HBM lags years (2026-07-26)
- caixinglobal.com — CXMT STAR Market debut scheduled July 27, board’s largest IPO (2026-07-24)
View all sources
- en.sedaily.com — DRAM price-fixing class action filed 2026-06-25, N.D. Cal., 17 plaintiffs, HBM-shift-as-cover to curtail DDR3/DDR4, ~700% over four years (2026-06-29)
- tomshardware.com — Same suit; ~90% combined DRAM share, Sherman Act §1, coordinated HBM shift allegation (2026-06-30)