LPDDR5X was supposed to be the cheap memory in your phone. Over the past month it became the memory three chipmakers chose to build AI silicon around – not because it is faster than HBM, but because the fast memory can no longer be gotten in the volume, at the price, or in the package these chips need.
The chips that left HBM out
AMD made the switch explicit. Its new Versal Premium Gen 2 “Memory-on-Package” adaptive SoCs carry up to 32GB of LPDDR5X in the package, at up to 288 GB/s, in a design AMD says uses up to 60% less board area. The significant part is what this memory replaces. AMD discontinued its prior Versal HBM line in September 2025, with reporting pointing to HBM2e supply as memory makers shifted their lines toward HBM3. AMD now presents LPDDR5X as a way to support a product lifecycle longer than 15 years without chasing the short refresh cycle of data-center HBM.
The old Versal HBM part ran at 840 GB/s. The new LPDDR5X design runs at 288 GB/s. That is roughly a two-thirds reduction in bandwidth, calculated from AMD’s published figures. This is not a direct performance upgrade. AMD is trading bandwidth for obtainable capacity, a smaller board footprint, a different packaging route, and a longer supply horizon.
AMD is not alone. Intel’s Crescent Island inference GPU, built on the Xe3P architecture, carries up to 480GB of LPDDR5X, capacity Intel positions as a response to memory shortages. Qualcomm’s Dragonfly AI200 inference rack is specified with 43TB of LPDDR5X and targets the market occupied by Nvidia, AMD, and Huawei. Nvidia is part of the same shift: its next-generation Vera CPU, the host processor in the Vera Rubin platform, uses LPDDR5X through SOCAMM modules developed with Samsung, SK Hynix, and Micron.
The company that sells HBM’s biggest destination is buying LPDDR5X for the other half of its own system. LPDDR5X is no longer only mobile memory. It is being recruited as a data-center inference tier.
The bottleneck LPDDR5X removes
The current bottleneck is not DRAM in the abstract. It is the combination of HBM availability and the advanced packaging needed to place HBM beside a compute die. HBM stacks DRAM dies vertically and connects them to the processor through a silicon interposer in a 2.5D package. TSMC’s CoWoS is the dominant flow. Its interposer, bonding, substrate, assembly, and qualification chain has constrained how many HBM accelerators can reach the market, with much of the available capacity committed to Nvidia.
LPDDR5X walks past that exact queue. It can be mounted on a conventional package substrate or supplied through a compact SOCAMM-style module. It requires neither an HBM silicon interposer nor a CoWoS slot. The equipment and material burden changes accordingly: the design gives up the dense, extremely wide HBM interface in exchange for a packaging flow without the same scarce HBM-specific steps.
Packaging does not become effortless. A new in-package memory design or SOCAMM module still needs electrical, thermal, mechanical, firmware, and customer qualification. Yield risk changes rather than vanishes. An integrated package can reduce board area and simplify the system-level memory layout, but a defect can affect the economics of a larger packaged assembly. The supplied evidence does not quantify those yields, so the defensible conclusion is precise: LPDDR5X removes the HBM interposer bottleneck, not every manufacturing or qualification constraint.
The workload distinction matters. HBM supplies much more bandwidth per accelerator and remains necessary for large training runs and bandwidth-bound prefill. Inference decode, which produces tokens sequentially, can place more weight on whether a model and its working state fit in memory. For a large mixture-of-experts model or a long context window, capacity can become the first gate. LPDDR5X is useful where avoiding an out-of-memory condition matters more than matching a top HBM accelerator’s bandwidth.
Capacity economics, with a bandwidth bill attached
The reported price ranges explain the attraction but are estimates, not universal quotations. Industry estimates place HBM3e near $15 per GB, with a broader HBM range of roughly $20 to $100 per GB depending on product and transaction. LPDDR and GDDR are reported below $10 per GB, while HBM3e is estimated at about three times commodity GDDR.
Intel’s announced 480GB LPDDR5X configuration holds about 2.5 times the on-package memory of a 192GB HBM accelerator. That ratio is a calculation from the stated capacities. At the cited estimate of about $15 per GB, 480GB of HBM would represent roughly $7,200 of memory alone. At less than $10 per GB, 480GB of LPDDR5X would be below $4,800. These calculations exclude packaging, yield, qualification, negotiated allocation, and other system costs, but they show why designers accept the bandwidth penalty.
The physical constraint may matter more than the arithmetic. A hypothetical 480GB HBM configuration cannot simply be substituted into a standard interposer design. Stack count, footprint, routing, power, and package limits intervene. LPDDR5X gives Intel a route to an announced capacity that is not practical through a conventional HBM accelerator package. For a capacity-bound job, this can be the difference between fitting the workload and failing to run it.
HBM keeps the training crown; LPDDR5X is taking an inference floor. For AMD, Intel, and Qualcomm, the value lies in reaching customers without depending on the HBM and CoWoS allocation that favors the largest incumbent. For hyperscalers and AI software vendors, the potential value is lower memory cost per deployed model and more capacity for long-context or mixture-of-experts inference. The risk is that lower bandwidth cuts throughput on workloads that cannot tolerate the difference.
The shift also changes the earlier DRAM squeeze as a cloud-versus-phone fight. Data-center inference is now bidding for the same low-power DRAM used by mobile devices. The route around one shortage becomes a new source of competition in another market.
The escape route becomes the new shortage
Here is the catch that the simple “AMD abandons HBM” framing misses: LPDDR5X is not a free exit from the memory crunch. It moves the constraint from HBM stacks and advanced packaging into low-power DRAM supply, module configuration, allocation, and price.
Nvidia’s Vera buildout reportedly made the company an LPDDR5X buyer on the scale of a major smartphone producer. Reporting says Nvidia reduced Vera Rubin’s SOCAMM2 capacity from 192GB to 96GB per module, using a two-high stack, after concluding that early allocations from Samsung, SK Hynix, and Micron would cover only about 60% of its estimated low-power DRAM requirement. This is reporting, not a supplied Nvidia statement. It is nevertheless a direct signal of the new bottleneck: the desired memory could not be secured, so the product configuration reportedly changed.
Reported prices moved in the same direction. DRAM contract prices rose by as much as 89% in the second quarter of 2026, while one edge-device bill of materials reportedly saw its LPDDR5X module cost rise from about $77 to $146. Neither figure means that every LPDDR5X buyer paid the same increase. Together, they show why the cost advantage cannot be treated as fixed. AMD, Intel, Qualcomm, and Nvidia can avoid the HBM packaging queue only to meet an allocation list for low-power DRAM.
The limits are clear. LPDDR5X does not displace HBM from training or bandwidth-bound prefill. It does not make a lower-bandwidth inference chip equivalent to a Blackwell-class accelerator on raw throughput. It does not guarantee a durable reduction in memory cost, because the data-center demand attracted by the lower price can bid that price upward.
The clean version of the thesis is narrower and stronger: the AI memory constraint is not being solved by LPDDR5X. It is being generalized across high-density DRAM tiers.
Who captures the value, and who carries the risk
Samsung, SK Hynix, and Micron are the clearest value owners. They can sell HBM into bandwidth-intensive accelerators while turning mobile-class LPDDR5X into a second AI memory franchise. If low-power DRAM remains constrained, they gain leverage over allocation and contract pricing. They also carry the execution burden of expanding output and qualifying server-oriented modules without neglecting existing mobile and client customers.
Accelerator vendors gain a route around the HBM and CoWoS bottleneck but inherit sourcing and workload-fit risk. AMD accepts a large published bandwidth reduction. Intel and Qualcomm must turn announced capacities into qualified, volume-shipping products. Nvidia can use SOCAMM to build a high-capacity host-memory tier, yet the reported configuration cut shows that even the industry’s largest AI buyer cannot assume it will obtain every desired LPDDR5X bit.
Hyperscalers and software vendors gain a higher-capacity inference tier that may improve deployment economics for memory-constrained models. Their risk is operational: capacity does not automatically translate into tokens per second, and rising LPDDR5X prices can weaken cost-per-token assumptions. Smartphone and PC makers receive little of that upside. They face the possibility that data-center buyers pull supply and supplier attention away from the products that used LPDDR5X first.
TSMC and other advanced-packaging participants sit in a mixed position. LPDDR5X inference designs can relieve part of the CoWoS and substrate bottleneck by moving selected workloads off the interposer path. They do not remove the HBM packaging demand generated by training. The likely result is workload segmentation, not the disappearance of advanced packaging.
What would prove the shift is durable
- LPDDR5X contract pricing through late 2026. Continued increases would erode the cost advantage that justified the switch. Quarterly contract data matters more than isolated spot-market movement.
- Whether Nvidia restores Vera SOCAMM2 capacity. The reported move from 192GB to 96GB per module is the clearest allocation signal in the supplied evidence. Restoration would suggest supply relief. Another reduction would indicate that low-power DRAM remains the gate.
- Intel Crescent Island and Qualcomm Dragonfly shipping in volume. Announced capacity is not delivered silicon. Customer qualification and volume shipment at the stated LPDDR5X capacities would confirm that the architecture has moved beyond product positioning.
- AMD’s sampling and production path. Reporting places Versal Premium Gen 2 Memory-on-Package sampling near the end of 2026 and production in the second half of 2027. Meeting that schedule would test whether the package, memory supply, and long-lifecycle argument survive qualification.
The deciding number is not a peak bandwidth specification. It is how much low-power DRAM the three major memory makers can direct into data-center packages without starving the phones and PCs that were LPDDR5X’s original market. AI demand has moved past HBM and its exotic packaging into a high-volume memory tier. The bottleneck moved with it.
This article is for informational and educational purposes only and does not constitute investment, financial, or legal advice.
Sources
- servethehome.com — AMD swaps HBM for LPDDR5X on Versal Premium Gen 2 MoP; discontinued Versal HBM Sept 2025 for HBM2e supply as makers shifted to HBM3; 15+ yr lifecycle rationale (2026-07)
- storagereview.com — Versal Gen 2 MoP: up to 32GB LPDDR5X, up to 288 GB/s, up to 60% less board area, sampling end 2026, production H2 2027 (2026-07)
- amd.com — AMD official blog announcing Versal Premium Gen 2 Memory on Package and its rationale (2026)
- techradar.com — Qualcomm Dragonfly AI200 inference rack with 43TB LPDDR5X, targets Nvidia/AMD/Huawei; AI250 High Bandwidth Compute (2026)
View all sources
- tomshardware.com — Intel Crescent Island Xe3P inference GPU, up to 480GB LPDDR5X, positioned to combat memory shortages (2026)
- amd.com — AMD Versal HBM series: up to 32GB HBM2e at 840 GB/s (prior-generation bandwidth baseline) (2026)
- semiengineering.com — HBM ~$20-100/GB, HBM3e ~$15/GB (~3x GDDR); LPDDR/GDDR under $10/GB; memory-tier suitability for AI (2026)
- anysilicon.com — CoWoS 2.5D packaging: HBM on silicon interposer next to compute die; advanced-packaging chain as the AI supply chokepoint (2026)
- tomshardware.com — LPDDR5X SOCAMM modules up to 128GB from Micron/SK Hynix (with Samsung), debut on Nvidia GB300; Nvidia Vera CPU uses LPDDR5X (2026)
- trendforce.com — Nvidia cuts Vera CPU memory configuration; persistent LPDRAM supply constraints and rising long-term demand (2026-06-10)
- thelec.net — Nvidia cuts SOCAMM2 from 192GB to 96GB (two-high stack) amid LPDDR shortage; ~60% of estimated LPDRAM needs met (2026)
- tomshardware.com — Nvidia LPDDR5X demand at smartphone-maker scale; DRAM prices up to 89% in Q2 2026; LPDDR5X module BOM ~$77 to ~$146 (2026)