Semiconductor
Hybrid-Bonded HBM: The Date SK Hynix Gave, and the One Samsung Hasn’t
SK Hynix put a name and a 2029-2030 date on hybrid-bonded HBM at Hot Chips 2026. Samsung's competing zHBM numbers still don't have one.
Semiconductor
Samsung zHBM: Memory Bonded to the Chip, Before the Line Exists
Samsung zHBM would hybrid-bond memory directly onto AI accelerator chips, but JEDEC just widened HBM4's own spec by 55 micrometers to avoid that same bond.
Semiconductor
HBM4 Turns Memory Into a Co-Designed System
HBM4 shifts the bottleneck from DRAM bandwidth to logic base dies, packaging, yield and customer qualification, changing who captures value and risk.
Semiconductor
High-NA EUV Is an Economic Decision Made One Layer at a Time
High-NA EUV economics depend on each layer: avoided multipatterning, yield and cycle-time gains must exceed scanner, mask and qualification cost.
Semiconductor
Both Spent Heavily. Only One Kept Free Cash Flow in the Tens of Billions.
Microsoft and Meta reported on the same day with comparable AI capex ambition. The same June quarter left Microsoft free cash flow in the tens of billions and
Semiconductor
CXMT IPO Funds DRAM Capacity, Not the High-Margin Tier
The CXMT IPO funds DRAM capacity nearing Micron's, but capacity isn't competitive supply - bit output, DDR5 cost, and HBM yield tell the real story.
Semiconductor
LPDDR5X Is AI’s New Inference Memory. The Shortage Came With It.
LPDDR5X is how AMD, Intel, and Qualcomm build AI inference chips around the HBM and CoWoS crunch - but AI demand is now rationing that memory tier too.
Semiconductor
Intel High-NA EUV Is a 14A Bet, Not a Panther Lake Win
Intel High-NA EUV shipped first in Panther Lake, but the real move is 14A: banking volume learning before the node where the tool actually earns its price.