Hybrid-Bonded HBM: The Date SK Hynix Gave, and the One Samsung Hasn’t

The Wall Every HBM Generation Hits First

At Hot Chips 2026 on August 23, SK hynix's VP of package engineering, Jaesik Lee, said the company does not expect hybrid bonding to be ready for HBM4E, the generation shipping next – pushing the industry's most anticipated packaging transition out to HBM5 at the earliest. The reason he gave was not cost and not customer demand. It was the bond itself: producing reliable copper-to-copper joints across 16 or 20 stacked memory dies, at that 775-micrometer height budget, remains an unresolved manufacturing problem.

SK hynix's current process – Mass Reflow Molded Underfill, or MR-MUF – will instead carry the company's 16-high HBM4 (already in customer qualification) and its HBM4E generation, extended all the way through Nvidia's next GPU platform.

The Business Already Riding on the Conservative Bet

This is not a hedge SK hynix is making with idle capacity. The company holds an estimated 70% of Nvidia's HBM orders for the Vera Rubin generation, and all of it is planned to ship on MR-MUF. SK hynix's own 2Q26 earnings release, published three and a half weeks before Hot Chips, said HBM4 mass production began that quarter for key customers, with a broader ramp planned for the second half, and that HBM4E has "demonstrated its differentiated technological edge" in samples already shipped.

On the same earnings call, the company said HBM4's mass-production yield and quality were "showing levels close to HBM3E, which has already entered a mature stage" – a maturity claim, not a disclosed percentage, but a real one: it is describing a process already earning revenue, not a lab result.

SK hynix is not standing still on the harder bond, either. In March, before any of this, it placed its first mass-production-grade hybrid-bonding equipment order – a roughly 20-billion-won ($14-15 million) inline system combining Applied Materials' polishing and plasma tools with a Besi hybrid die bonder, the same tool pairing already running in volume at TSMC to build AMD's 3D V-Cache. An industry official close to the order called it preparation for "the next-next generation," not the current one.

That is the shape of a company buying the equipment years before it plans to need it commercially – confident about the direction, unwilling to bet the current product cycle on the timing.

Samsung's Numbers, and Where They Haven't Appeared Yet

Samsung took the opposite side of the same conference. Its zHBM concept goes further than the DRAM-to-DRAM hybrid bond SK hynix just deferred – it proposes stacking the memory directly onto the compute die itself, eliminating the interposer between them entirely, in a wafer bond that has to survive next to well over 1,000 watts of logic heat rather than sit beside it.

Trade press covering Samsung's Hot Chips technical session reported specific numbers: 70% higher power efficiency and 230% greater DRAM bandwidth than a standard HBM4e stack, with one cited example showing four zHBM stacks paired with a 1,200-watt GPU saving roughly 100 watts.

Here is the detail the headline numbers skip past. Samsung's own official channel – a company tech-blog post about zHBM from its FMS 2026 keynote, published nine days before Hot Chips – describes the same architecture only in qualitative terms: it "integrates logic and memory in 3D to reduce the physical distance data must travel," with no power-efficiency percentage, no bandwidth multiplier, and no production timeline attached. The 70% and 230% figures exist, independently reported by more than one outlet covering the same technical session. They do not yet exist in anything Samsung itself has published.

Data

The Gap That Would Actually Prove Someone Right

The honest counter to all of this is that hybrid bonding is not experimental technology in general. TSMC has been hybrid-bonding AMD's 3D V-Cache in high volume since the Ryzen 7 5800X3D shipped in 2022, at sub-10-micron pitch, with no solder bump in the joint at all. A company with Samsung's process resources could plausibly have real internal validation behind its zHBM numbers and simply not have chosen to publish it through an investor-facing channel yet – corporate disclosure timing is not the same thing as technical readiness.

But that counter cuts in a specific, checkable direction: it says the gap is a disclosure gap, not a physics gap, and disclosure gaps close on their own schedule if the numbers are real. Samsung publishing its own 70% and 230% figures through an official newsroom or investor release, with a production date attached, would close it. So would a named accelerator customer announcing an actual hybrid-bonded HBM qualification ahead of SK hynix's stated window, or a second hybrid-bonding equipment supplier shipping production-grade tools faster than Besi and Applied Materials currently are. None of those has happened yet.

What has happened is that the company selling into next year's GPU platform chose the process it already knows how to run, and said so on the record with a name and a date attached – and the company with the more dramatic numbers has, so far, only said so through someone else's coverage of a conference room.